80386 support overall ___ addressing modes to facilitate efficient execution of higher level language programs.
80386 provides eleven addressing modes for efficient high-level language execution.
Ref: Microprocessor Architecture by Ramesh Gaonkar
IISc MODULE 8 - HIGH END PROCESSORS
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80386 support which type of descriptor table from the following?
Global descriptor table holds system-wide segment descriptors for protected mode.
Ref: Microprocessor Architecture by Ramesh Gaonkar
To prevent another master from taking over the bus during a critical operation, the 486 can assert its _____ signal.
LOCK# or PLOCK# locks the bus against other masters during critical operations.
Ref: Microprocessor Architecture by Ramesh Gaonkar
_____ is used to control the cache with two new control bits not present in the 80386 microprocessor. What are the bits
CR0 CD and NW bits control the 486 8K on-chip cache.
Ref: Microprocessor Architecture by Ramesh Gaonkar
A new signal group on the 80486 is the ______.
486 adds the PARITY group comprising DP0-DP3 and PCHK signals.
Ref: Microprocessor Architecture by Ramesh Gaonkar
The ___ bit decides whether it is a system descriptor or code/data segment descriptor
S bit distinguishes system descriptors from code or data descriptors.
Ref: Microprocessor Architecture by Ramesh Gaonkar
The interrupt vector table of 80386 has been allocated ______ space starting from _______ to _______.
256 vectors times four bytes occupy 1 Kbyte from 00000H to 003FFH.
Ref: Microprocessor Architecture by Ramesh Gaonkar
Virtual Mode Flag bit can be set using ____ instruction or any task switch operation only in the _____ mode
VM flag is set by IRET or task switch only in protected mode.
Ref: Microprocessor Architecture by Ramesh Gaonkar
If ______ input pin of 80386 if activated, allows address pipelining during 80386 bus cycles.
NA, Next Address, requests the next address early for pipelining.
Ref: Microprocessor Architecture by Ramesh Gaonkar
Segmentation unit allows segments of _____ size at maximum.
80386 segments can reach 4 Gbytes maximum with 32-bit offset.
Ref: Microprocessor Architecture by Ramesh Gaonkar
